Embodiments of the present disclosure relate to semiconductor memory devices.
Computer systems or electronic communication systems continue to advance in parallel with increases in the storage capacity and lower fabrication cost of the semiconductor memory devices used in such systems. In particular, a high integration density of the semiconductor memory devices may lead to a high capacity of data storage thereof. The semiconductor memory devices, for example, dynamic random access memory (DRAM) devices may be configured to include a plurality of word lines and a plurality of bit lines which are arrayed in rows and columns to intersect each other, and a plurality of memory cells may be disposed at respective ones of cross points of the word lines and the bit lines. Each of the memory cells of the DRAM devices may be configured to include a single cell transistor and a single capacitor, and the memory cells of the DRAM devices may constitute one or more cell blocks. Operations of the DRAM devices may be briefly described hereinafter.
If a complementary (e.g., inversed) row address strobe (/RAS) signal is enabled during an active operation, a row address signal supplied through a row address buffer may be decoded to execute a row decoding operation that selects one of word lines in a cell block. In such a case, if data in memory cells electrically connected to the selected word line are loaded on bit line pairs including bit lines and complementary bit lines, a signal informing of a point of time that sense amplifiers operate may be enabled to drive a sense amplifier drive circuit of a cell block which is selected by the row address signal. In addition, bias potentials of the sense amplifiers may be changed into a core potential (Vcore) or a ground potential (Vss) by the sense amplifier drive circuit, and the sense amplifiers may operate. If the sense amplifiers operate, a small potential difference between a bit line potential and a complementary bit line potential may be amplified to have a large potential difference.
Subsequently, if a read operation is executed, at least one of the bit line data amplified by the sense amplifiers may be transmitted to an input/output (I/O) line through a column transfer transistor which is selected and turned on by a column address signal. Meanwhile, if a write operation is executed, a data supplied through the I/O line may be loaded on the bit line through the column transfer transistor which is selected and turned on by a column address signal, and the data on the bit line may be stored in a memory cell through at least one of cell transistors which are turned on by a selected word line.
As described above, the semiconductor memory devices may operate in a write mode to store data into the memory cells, or a read mode to read out the data stored in the memory cells. When the write operation and the read operation are executed, a plurality of internal signals may be generated in the semiconductor memory device.